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[CSharp] pof2jed

Description: MAX+PLUS II 生成pof文件到Atmel15xx系列jed下载格式的转换软件windows版。-MAX PLUS II generation POF documents to the Atmel15xx series jed download format windows version of the software conversion.
Platform: | Size: 1270784 | Author: yibu | Hits:

[Communication] maxplus2

Description: 关于CPLD的文章 不错的! 可以给菜菜参考下-article on the CPLD good! Can either under reference
Platform: | Size: 17325056 | Author: 许辉 | Hits:

[Other] cpusourcecodeusingmaxplus

Description: 一个用max+plus II写的很小的源码。简单但对初学还行吧-max plus one with a small II was the source. Simple but for beginners it is also OK
Platform: | Size: 1024 | Author: 风 | Hits:

[MiddleWare] pwm_VerilogHDLV1.1

Description: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Platform: | Size: 232448 | Author: wjz | Hits:

[Documents] 040207

Description: 数字钟电路系统由主体电路和扩展电路两大部分组成。其中，主体电路完成数字钟的基本功能，扩展电路完成数字钟的扩展功能。用MAXPLUSⅡ进行电路设计与仿真.-digital clock circuit system from the main circuit and the circuit extended two major components. Among them, the main circuit digital clock to complete the basic functions, expanding digital clock circuit to complete the expansion function. II FPGA used for circuit design and simulation.
Platform: | Size: 455680 | Author: 李明 | Hits:

[Applications] C_10

Description: VHDL实例,在MAX+Plus+II下开发-VHDL example, the MAX II Plus under development
Platform: | Size: 1280000 | Author: 孙庆波 | Hits:

[VHDL-FPGA-Verilog] Electronwatch

Description: This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.
Platform: | Size: 1024 | Author: 施红希 | Hits:

[Other] f_add

Description: 本文件包是在MAX+plus II 软件环境下实现半加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve a half-adder logic function
Platform: | Size: 12288 | Author: 罗理平 | Hits:

[Other] h_adder

Description: 本文件包是在MAX+plus II 软件环境下实现全加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve full adder logic function
Platform: | Size: 13312 | Author: 罗理平 | Hits:

[Other] mendianlu

Description: 本文件包是在MAX+plus II 软件环境下验证门电路的逻辑功能-This document packet was MAX+ Plus II software environment to verify the logic function circuit door
Platform: | Size: 12288 | Author: 罗理平 | Hits:

[Other] count

Description: 本文件包是在MAX+plus II 软件环境下实现计数器的逻辑功能-This document packet was MAX+ Plus II software environment counters realize the logic function
Platform: | Size: 58368 | Author: 罗理平 | Hits:

[VHDL-FPGA-Verilog] VHDLandDigitalCircuitDesign

Description: 本书系统地介绍了一种硬件描述语言，即VHDL语言设计数字逻辑电路和数字系统的新方法。这是电子电路设计方法上一次革命性的变化，也是迈向21世纪的电子工程师所必须掌握的专门知识。本书共分12章，第l章---第8章主要介绍VHDL语言的基本知识和使用VHDL语言设计简单逻辑电路的基本方法；第9章和第10章分别以定时器和接口电路设计为例，详述了用VHDL语言设计复杂电路的步骤和过程；第11章简单介绍了VHDL语言93版和87版的主要区别；第12章介绍了MAX+plus II的使用说明。 本书以数字逻辑电路设计为主线，用对比手法来说明数字逻辑电路的电原理图和VHDL语言程序之间的对应关系，并列举了众多的实例。另外，还对设计中的有关技术，如仿真、综合等作了相应说明。本书简明扼要，易读易懂。它可作为大学本科和研究生的教科书，也可以作为一般从事电子电路设计工程师的自学参考书。
Platform: | Size: 18693120 | Author: qinlei | Hits:

[VHDL-FPGA-Verilog] f_adder

Description: 在EDA的MAX+PLUS II开发环境下用VHDL编写的全加器-In the EDA
Platform: | Size: 56320 | Author: 林超勇 | Hits:

[VHDL-FPGA-Verilog] ADD

Description: 在MAX+PLUS II环境下用VHDL编写的加法器-In MAX+ PLUS II environment prepared using VHDL Adder
Platform: | Size: 34816 | Author: 林超勇 | Hits:

[MPI] exercise1

Description: 在软件MAX+plus II环境中，设计了一台RISC模型机，具有以下功能：输入包含10个整数（无符号数）的数组M，按从小到大的顺序输出这10个数。-In terms of software MAX+ Plus II environment, the design model of a RISC machine, has the following features: input contains 10 integer (unsigned number) of the array M, according to the order from small to large number of the output of these 10.
Platform: | Size: 937984 | Author: 陈自分 | Hits:

[VHDL-FPGA-Verilog] FPGAforDLC

Description: 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
Platform: | Size: 62464 | Author: yangj2 | Hits:

[VHDL-FPGA-Verilog] MyProject

Description: 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3，原理图源文件保存在MyProject目录中，为138decoder.gdf，另有我写的实验报告，呵呵，适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyProject directory for 138decoder.gdf, otherwise I write experimental reports, Ha ha, suitable for simulation of induction
Platform: | Size: 224256 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] Design_of_Traffic_Light_Control_System_Base_on_FPG

Description: 用VHDL 语言设计交通灯控制系统, 并在MAX+PLUS II 系统对FPGA/ CPLD 芯片进行下载, 由于生成的是集成化的数字电 路, 没有传统设计中的接线问题, 所以故障率低、可靠性高, 而且体积小。体现了EDA 技术在数字电路设计中的优越性。-The design method of traffic light control system by using Very- High- Speed Integrated Circuit Hardware Description Language (VHDL) is introduced, and the downloading of the controller design to the FPGA/ CPLD chip in MAX+PLUS II is fulfilled. As FPGA/ CPLD chips are based on large scale IC and there are no connection problems in the presented circuit, so the chips are re1iable and faults are less prone to happen, which shows the advantages of the EDA technology in digital circuits design.
Platform: | Size: 72704 | Author: li | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[OpenGL program] MAX_Plus_II

Description: MAX_Plus_II应用超级教程 里边内容很多的 和它有关的一些器件，还有应用在其上的一些东东 总之不错-Super Guide MAX_Plus_II inside the contents of the application and it is a lot of some of the devices, as well as apply it to some good short Dongdong
Platform: | Size: 3318784 | Author: 李白 | Hits:
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